Failure Analysis Services
EAG offers IC failure analysis services in support of our client's need to achieve high quality and reliable electronic products. Our commitment to this goal is demonstrated either by providing services designed to complement and supplement our customers' internal capabilities or by providing a source for comprehensive IC failure analysis support. EAG has optimized service offerings to provide our clients with maximum value by leveraging advanced analytical techniques capabilities and proven investigative methodology with broad engineering knowledge and expertise. EAG is the leader in providing such a breadth of services, and is unmatched in accessibility through fully integrated laboratory locations around the world.
Capabilities
EAG possesses a comprehensive array of advanced tools and techniques available for performing failure analysis on integrated circuits and other electronic devices.
Services
The ultimate goal in failure analysis is to arrive at an accurate determination of the cause of the failure. EAG has developed a proven, methodical process of failure analysis that is efficient but can be customized for your needs. For all levels of effort, EAG uses advanced tools and techniques coupled with expert interpretation to provide insight into the investigation and product failure.
- Technique only - This is a focused approach designed to include one or more specific analysis techniques to understand, characterize or determine a defined task/need.
- Level 1 - The scope of the analysis includes failure verification, non-destructive package integrity examination and internal visual examination.
- Level 2 - This stage of the investigation uses fault isolation techniques to localize the failure to a specific site on a sample, providing valuable information pointing to a design, product, or package issue.
- Level 3 - The scope of this effort incorporates designing and applying the appropriate FA methodology to physically identify and characterize the failure mechanism and ultimately determine root cause.
Expertise
EAG builds strong relationships and confidence with our clients, starting with engineer-to-engineer interaction to discuss and understand your goals, objectives and urgency. We understand the challenges and difficulties with leading edge technologies. EAG engineers are knowledgeable in today's advanced product technologies and are experts in IC failure analysis. EAG's network of laboratories ensures we can provide the best analysis techniques and expertise to help solve problems, leading investigations for a wide range of technology disciplines and industries.
- Devices and Technology: ASIC, discretes, passives, RF, Advanced CMOS, III-V, GaAs, LED, Solar cells,
- Product Life Cycle: Design debug, Reliability Foundry, Package assembly, Final test yield, Field / Customer return
- Systems Level Analysis: Parametric test, PCBA, Solder joint integrity, technical consultation
- Construction and Competitor analysis
- Counterfeit / Authenticity
- Materials analysis, Cross sectioning, Tear down
Failure Analysis Tools and Techniques
Electrical Analysis
- Fine pitch BGA and high pin count capability
- Curve trace
- Parametric and functional test
- Device characterization
- Time Domain Reflectometry (TDR)
- Transmission Line Pulse (TLP)
Package Integrity
- External optical examination
- Scanning Acoustic Microscopy (CSAM)
- Real Time X-ray analysis
- Thermal resistance measurement
Decapsulation
- Cu wire
- Jet etch/chemical
- De-lid
- Oxygen plasma
Optical Inspection
- Bright and dark field imaging
- Nomarski Differential Interference Contrast (DIC)
- Near-IR inspections through Silicon
Fault Isolation
- Front side and Backside analysis
- Laser Timing Probe (LTP)
- Laser Signal Injection Microscopy (XIVA and OBIRCH)
- Infrared (IR) Thermography (hot spot and temperature mapping)
- Light Emission Microscopy (LEM) / EMMI
- Microprobing and Picoprobing
Physical Analysis
- Reactive Ion Etch (RIE), wet and parallel lap de-processing
- Scanning Electron Microscopy (SEM) / Energy Dispersive X-ray Spectroscopy (EDS)
- Scanning Transmission Electron Microscopy (STEM)
- Dual Beam Focused Ion Beam (DB FIB)
- Metallurgical cross-sectioning
Typical Failure Analysis Investigations
- FIB / circuit debug
- Thermal resistance measurements
- Temperature mapping
- ESD snap-back resistance
- Latch-up initiation site
- Resistive vias
- Mold compound delamination
- Lithography pattern defects
- Die attach fillet height
- Flip chip under fill voiding
- ESD drain/source breakdown
- Gate oxide breakdown
- Electrical overstress
- Contamination and corrosion
- Electromigration
- Solder joint integrity
Failure Mechanisms
Failure Analysis Levels
Technique Only
This type of analysis is driven mainly by the requirement or intent to understand, characterize or determine a defined goal rather than the need for a full investigation effort. This analysis may only involve one or a few of the tools or techniques (a la carte) to obtain a specific answer or data point. Because the scope of this type effort is well defined, it can yield quick results that can be used to design a more comprehensive analysis approach.
Level 1
A majority of package defects and electrical over stress (EOS) mechanisms can be easily identified during this fast, but comprehensive initial investigation. The scope of this analysis includes electrical failure verification (curve trace, bench testing, TDR, etc), non-destructive package integrity examination (X-ray and CSAM), package decapsulation, and internal visual examination. The obtained results can not only identify and define observable failures, but can also help eliminate other possible causes and sources, such as manufacturing and handling, which will be used to outline the next applicable approach/techniques to follow-on the investigation as needed.
Level 2
The main focus of this level of analysis is to isolate and localize the specific failure or defect site, e.g. ESD protection vs. input buffer. Typical fault isolation tools used are LEM, LSIM, and IR. But additionally, we have a comprehensive and progressive set of specialty capabilities such as Pico/microprobing to supplement during the more complex and intricate analysis approaches. Even with the advances in IC packaging (flip chips, modules, CSP, stacked die, etc) our experienced engineers develop creative ways to mitigate challenges in order to utilize the most effective FA techniques.
Level 3
This level is typically defined as "full" analysis. The scope of this effort incorporates the appropriate FA methodology to physically identify and characterize the failure mechanism, and help determine root cause. The specifically utilized techniques and tools will be determined by the failure mode and IC construction. For ESD failures, the work may entail backside XIVA localization, deprocessing and SEM inspection, while process defects may require Dual FIB, SEM/EDS and/or S/TEM. But whatever your needs and failures, our FA experts equipped with the most progressive tool sets and techniques can provide the solution.
Product Life Cycle
- Design / Debug
- New Silicon / Design
- Package Assembly
- Power management Studies
- Qualification
- ESD / Latch-up
- Operating Life
- Environmental Stress
- Production
- Wafer sort Yield
- Final test Yield
- Yield improvement
- Applications
- System Level
- PCB manufacturing yield
- Field
